Verification Engineer

Verification Engineer Miejsce pracy: Warszawa Technologies we use Expected SystemVerilog UVM ASIC SoC RTL AXI AHB APB PCIe Ethernet Cadence Xcelium Synopsys VCS Siemens Questa DVE Verdi Python Perl Bash About the project We are looking for an experienced Verification Engineer with approximately 5 years of hands-on experience to own block and subsystem-level functional verification. In this role, you will build and enhance UVM-based testbenches, execute coverage-driven verification, and collabor…