ID oferty: 720557
Źródło: adzuna
Kategoria: IT
Opis: Senior Verification Engineer (UVM/SystemVerilog) Miejsce pracy: Warszawa Technologies we use Expected UVM SystemVerilog Optional C C++ Python SystemC This is how we organize our work This is how we work at the client's site Your responsibilities Perform the full range of functional verification activities. Develop verification environments from scratch, including drivers, monitors, scoreboards, and coverage models. Integrate Verification IPs (VIPs) for protocols such as DDR, PCIe, and AXI. Defi…
Utworzono: 16.10.2026 22:23